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| TECHNICAL DATA IW4015B Dual 4-Stage Static Shift Register High-Voltage Silicon-Gate CMOS The IW4015B consists of two identical, independent, 4-stage serial-input/parallel-output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. "Q" outputs are available from each of the four stages on both registers. All register stages are D-type, master-slave flip-flops. The logic level present at the DATA input is transferred into the first register stage and shifted over one stage at each positive-going clock transition. Resetting of all stages is accomplished by a high level on the reset line. Register expansion to 8 stages using one IW4015B package, or to more than 8 stages using additional IW4015B's is possible. * Operating Voltage Range: 3.0 to 18 V * Maximum input current of 1 A at 18 V over full packagetemperature range; 100 nA at 18 V and 25C * Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply ORDERING INFORMATION IW4015BN Plastic IW4015BD SOIC TA = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Clock Data L H PIN 16=VCC PIN 8= GND X X X Reset L L L H Outputs Q1 L H L Qn Qn-1 Qn-1 L No change X = don't care 24 IW4015B MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN PD PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Power Dissipation per Output Transistor Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +20 -0.5 to VCC +0.5 -0.5 to VCC +0.5 10 750 500 100 -65 to +150 260 Unit V V V mA mW mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min 3.0 0 -55 Max 18 VCC +125 Unit V V C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 25 IW4015B DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Symbol VIH Parameter Minimum High-Level Input Voltage Test Conditions VOUT= 0.5 V or VCC - 0.5V VOUT= 1.0 V or VCC - 1.0 V VOUT= 1.5 V or VCC - 1.5V V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 18 5.0 10 15 20 5.0 10 15 5.0 5.0 10 15 Guaranteed Limit -55C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 0.1 5 10 20 100 0.64 1.6 4.2 -2 -0.64 -1.6 -4.2 25C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 0.1 5 10 20 100 0.51 1.3 3.4 -1.6 -0.51 -1.3 -3.4 125 C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 1.0 150 300 600 3000 0.36 0.9 2.4 mA -1.15 -0.36 -0.9 -2.4 Unit V VIL Maximum Low -Level VOUT= 0.5 V or VCC - 0.5V Input Voltage VOUT= 1.0 V or VCC - 1.0 V VOUT= 1.5 V or VCC - 1.5V Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) VIN=GND or VCC V VOH V VOL VIN=GND or VCC V IIN ICC VIN= GND or VCC VIN= GND or VCC A A IOL Minimum Output Low VIN= GND or VCC (Sink) Current UOL=0.4 V UOL=0.5 V UOL=1.5 V Minimum Output VIN= GND or VCC High (Source) Current UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V mA IOH 26 IW4015B AC ELECTRICAL CHARACTERISTICS(CL=50pF, RL=200k, Input tr=tf=20 ns) VCC Symbol tmax Parameter Maximum Clock Frequency (Figure 1) V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 3 6 8.5 320 160 120 400 200 160 200 100 80 Guaranteed Limit -55C 25C 3 6 8.5 320 160 120 400 200 160 200 100 80 7.5 125C 1.5 3 4.25 640 320 240 800 400 320 400 200 160 Unit MHz tPHL, tPLH Maximum Propagation Delay, Clock to Q (Figure 1) Maximum Propagation Delay, Reset to Q (Figure 2) Maximum Output Transition Time, Any Output (Figure 1) Maximum Input Capacitance ns tPHL ns tTHL, tTLH ns CIN pF TIMING REQUIREMENTS(CL=50pF, RL=200 k, Input tr=tf=20 ns) VCC Symbol tw Parameter Minimum Pulse Width, Clock (Figure 1) V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 180 80 50 200 80 60 70 40 30 0 0 0 15 6 2 Guaranteed Limit -55C 25C 180 80 50 200 80 60 70 40 30 0 0 0 15 6 2 125C 360 160 100 400 160 120 140 80 60 0 0 0 30 12 4 Unit ns tw Minimum Pulse Width, Reset (Figure 2) ns tsu Minimum Setup Time, Data to Clock (Figure 3) Minimum Hold Time, Clock to Data (Figure 3) Maximum Input Rise and Fall Time (Figure 1) ns th ns tr, tf s 27 IW4015B Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms EXPANDED LOGIC DIAGRAM ( 1/2 of the Device) 28 |
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